The delay bound in system on chips (SoC) represents the worst-case traverse time of on-chip\ncommunication. In network on chip (NoC)-based SoC, optimizing the delay bound is challenging due\nto two aspects: (1) the delay bound is hard to obtain by traditional methods such as simulation; (2) the\ndelay bound changes with the different application mappings. In this paper, we propose a delay\nbound optimization method using discrete firefly optimization algorithms (DBFA). First, we present\na formal analytical delay bound model based on network calculus for both unipath and multipath\nrouting in NoCs. We then set every flow in the application as the target flow and calculate the\ndelay bound using the proposed model. Finally, we adopt firefly algorithm (FA) as the optimization\nmethod for minimizing the delay bound. We used industry patterns (video object plane decoder\n(VOPD), multiwindow display (MWD), etc.) to verify the effectiveness of delay bound optimization\nmethod. Experiments show that the proposed method is both effective and reliable, with a maximum\noptimization of 42.86%.
Loading....